1. Field of the Invention
The present invention relates to a wafer-scale package structure for rearranging and packaging electrode pads in a lump and in the form of a wafer, and a circuit board used in such a wafer-scale package structure.
The present application is based on Japanese Patent Application No. Hei. 10-202227 which is incorporated herein by reference.
2. Description of the Related Art
With miniaturization and realization of high-performance in electronic equipments in recent years, semiconductor devices constituting the electronic equipments and multilayer printed-wiring boards mounted with the semiconductor devices have been required to be small and thin and to have high performance and high reliability. Under such conditions, packages have been miniaturized, and semiconductor devices which are substantially as large as chips and called chip-size packages (CSPs) have been developed. Various methods have been proposed for the chip-size packages, but usually, chips subjected to dicing are packaged individually one by one. For example, often used is a method in which fine electrode pads on each chip are rearranged in the form of a grid and sealed with resin or the like.
However, since chips cut out of a wafer are packaged individually one by one, the above-mentioned method has problems that the productivity deteriorates, the cost increases, and so on.